The 8051 Microcontroller and Embedded Systems, Volume 1For courses teaching the 8051 Microcontoller. This book uses a step-by-step approach to teach the fundamentals of assembly language programming and interfacing of the 8051 microcontroller. It uses many examples to clarify concepts. Simple, concise examples are utilized to show what action each instruction performs, then a sample is provided to show its application. This text provides a comprehensive understanding of the internal organization of the 8051 registers and resources in a way that sheds the student's fear of assembly language. Whether students become designers of stand-alone systems or complex embedded systems, they will find this text a useful resource. |
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Page 410
Register Bank selector bit 1 ( SEE NOTE 1 ) . R.SO PSW.3 OV PSW.2 Register Bank selector bit 0 ( SEE NOTE 1 ) . Overflow Flag . PSW.1 User definable flag . P PSW.0 Parity flag . Set / cleared by hardware each instruction cycle to ...
Register Bank selector bit 1 ( SEE NOTE 1 ) . R.SO PSW.3 OV PSW.2 Register Bank selector bit 0 ( SEE NOTE 1 ) . Overflow Flag . PSW.1 User definable flag . P PSW.0 Parity flag . Set / cleared by hardware each instruction cycle to ...
Page 415
BIT ADDRESSABLE Table 7 T2CON INTERNAL EXTERNAL MODE CONTROL CONTROL ( NOTE 1 ) ( NOTE 2 ) 16 - bit Auto - Reload OOH 08H 16 - bit Capture 01H 09H BAUD rate generator receive & transmit same baud rate 34H 36H 24H 26H 14H 16H 8052 Only ...
BIT ADDRESSABLE Table 7 T2CON INTERNAL EXTERNAL MODE CONTROL CONTROL ( NOTE 1 ) ( NOTE 2 ) 16 - bit Auto - Reload OOH 08H 16 - bit Capture 01H 09H BAUD rate generator receive & transmit same baud rate 34H 36H 24H 26H 14H 16H 8052 Only ...
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( NOTE 1 ) . SM2 REN TB8 RB8 TI RI SCON . 5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3 , if SM2 is set to 1 then RI will not be activated if the received 9th data bit ( RB8 ) is 0.
( NOTE 1 ) . SM2 REN TB8 RB8 TI RI SCON . 5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3 , if SM2 is set to 1 then RI will not be activated if the received 9th data bit ( RB8 ) is 0.
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Contents
CHAPTERS | 1 |
The 8051 Microcontrollers | 23 |
THE 8051 MICROCONTROLLERS 223 Section 1 1 Microcontrollers and Embedded Processors | 24 |
Copyright | |
19 other sections not shown
Other editions - View all
The 8051 Microcontroller and Embedded Systems: Using Assembly and C Mazidi Muhammad Ali No preview available - 2007 |
Common terms and phrases
ACALL ACALL DELAY addr addressing mode ASCII Assembly language baud rate binary bit addresses carry flag Chapter CJNE connected convert data pins decimal decoder discussed DJNZ DPTR EPROM Example execution external interrupt Figure flag bit frequency I/O ports instruction INT1 Intel interfacing interrupt vector table jump latch LCALL LJMP load logic loop machine cycle memory chip memory location microcontroller microprocessor MOV P1 MOV RO MOVX Notice NV-RAM on-chip ROM opcode operand output pointer program counter PSEN pull-up resistors pulse RAM location register bank reset Review Questions SBUF SECTION serial communication SETB TR1 Show signal SJMP Solution square wave stack stepper motor stop bit SUBB subroutine target address TCON timer Timer/counter TMOD transfer transistors True or false voltage Write a program
Bibliographic information
| Title | The 8051 Microcontroller and Embedded Systems, Volume 1 The 8051 Microcontroller and Embedded Systems, Muhammad Ali Mazidi |
| Authors | Muhammad Ali Mazidi, Janice Gillispie Mazidi |
| Edition | illustrated |
| Publisher | Prentice Hall, 2000 |
| Original from | the University of Michigan |
| Digitized | 5 Aug 2011 |
| ISBN | 0138610223, 9780138610227 |
| Length | 435 pages |
| Export Citation | BiBTeX EndNote RefMan |