Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous PlatformsThe main intention of this book is to give an impression of the state of the art in energy-aware task-scheduling-related issues for very dynamic emb- ded real-time processing applications. The material is based on research at IMEC in this area in the period 1999–2006, with a very extensive state-- the-art overview. It can be viewed as a follow-up of the earlier “Modeling, veri?cation and exploration of task-level concurrency in real-time embedded systems” book [234] that was published in 1999 based on the task-level m- eling work at IMEC. In order to deal with the stringent timing requirements, the cost-sensitivity and the dynamic characteristics of our target domain, we have again adopted a target architecture style (i. e. , heterogeneous mul- processor) and a systematic methodology to make the exploration and op- mization of such systems feasible. But this time our focus is mainly on p- viding practical work ?ow out of the (abstract) general ?ow from previous book and also the relevant scheduling techniques for each step of this ?ow. Our approach is very heavily application-driven which is illustrated by several realistic demonstrators. Moreover, the book addresses only the steps above the traditional real-time operating systems (RTOS), which are mainly focused on correct solutions for dispatching tasks. Our methodology is nearly fully independent of the implementations in the RTOS so it is va- able for the realization on those existing embedded systems where legacy applications and underlying RTOS have been developed. |
Contents
1 | |
15 | |
System Model and Work Flow 35 | 34 |
Basic DesignTime Scheduling | 51 |
Scalable DesignTime Scheduling 109 | 108 |
Fast and Scalable Runtime Scheduling | 135 |
Handling of Multidimensional Pareto Curves | 151 |
RunTime Software Multithreading | 163 |
Fast Sourcelevel Performance Estimation | 177 |
Handling of TaskLevel Data Communication and Storage 195 | 194 |
Demonstration on Heterogeneous Multiprocessor SoCs | 225 |
Conclusions and future research work | 239 |
References 249 | 248 |
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Common terms and phrases
algorithm application approach architecture assignment becomes behavior better chapter combination compared comparison complexity computation considered constraints cost data structures deadline decoder decomposition dependencies design-time scheduling detailed dynamic effective efficient energy consumption energy-cost estimation example execution exhaustive search exist experiments exploration Figure final flow function further given gives graph handle heterogeneous illustrated implemented important improve increase initial input interleaving kernel heuristic mapping memory method operating optimal parallel Pareto curve performance phase platform possible presented priority problem proc processing processor produced proposed pruning range real-time reduce resource run-time scheduler scenarios selection shows simulator single solution space static step structures Table task technique thread frame thread nodes thread partitions time-budget tion trade-off voltage weight
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