The Practical Xilinx Designer Lab Book: Version 1.5 |
Contents
Programmable Logic Design Techniques | 23 |
Combinational Logic | 69 |
Modular Designs and Hierarchy | 101 |
Copyright | |
10 other sections not shown
Other editions - View all
The Practical XILINX Designers Lab Book, Volumes 1-2 David E. Van den Bout No preview available - 1998 |
Common terms and phrases
1-bit adder ABEL code argument of XSPORT asynchronous bits BO argument Boolean buffer button carry flag chip circuitry clock edge clock input clock signal COMPONENT connect CPLD data bus drink_state DWARF ELSIF equations external RAM FIFO flip-flop Foundation Series FPGA FPLD gate delays GNOME Hooterville Hwy3 IBUF increment inputs and outputs instruction decoder instruction register interface ISTYPE REG JTAG Krunk LED decoder LED segment Listing load machine Mayberry memory location menu item module multiplexer netlist next_st NODE ISTYPE OBUF opcode operand operation output bus parallel port parity PIN ISTYPE PORT MAP program counter Project Manager window Q output reset ripple-carry adder shown in Figure signal Siler City simulation STD_LOGIC STD_LOGIC_VECTOR 3 DOWNTO Trip-Genie tristate truth table VHDL code VHDL version Waveform Viewer Xilinx XS40 Board XS95 Board zero flag