Computer Architecture: Software Aspects, Coding, and Hardware

Front Cover
CRC Press, Dec 19, 2017 - Computers - 456 pages

With the new developments in computer architecture, fairly recent publications can quickly become outdated. Computer Architecture: Software Aspects, Coding, and Hardware takes a modern approach. This comprehensive, practical text provides that critical understanding of a central processor by clearly detailing fundamentals, and cutting edge design features. With its balanced software/hardware perspective and its description of Pentium processors, the book allows readers to acquire practical PC software experience. The text presents a foundation-level set of ideas, design concepts, and applications that fully meet the requirements of computer organization and architecture courses.

The book features a "bottom up" computer design approach, based upon the author's thirty years experience in both academe and industry. By combining computer engineering with electrical engineering, the author describes how logic circuits are designed in a CPU. The extensive coverage of a micprogrammed CPU and new processor design features gives the insight of current computer development.

Computer Architecture: Software Aspects, Coding, and Hardware presents a comprehensive review of the subject, from beginner to advanced levels. Topics include:


o Two's complement numbers o Integer overflow
o Exponent overflow and underflow o Looping
o Addressing modes o Indexing
o Subroutine linking o I/O structures
o Memory mapped I/O o Cycle stealing
o Interrupts o Multitasking
o Microprogrammed CPU o Multiplication tree
o Instruction queue o Multimedia instructions
o Instruction cache o Virtual memory
o Data cache o Alpha chip
o Interprocessor communications o Branch prediction
o Speculative loading o Register stack
o JAVA virtual machine o Stack machine principles

 

Contents

I
11
II
11
III
11
IV
16
V
24
VI
25
VII
28
VIII
33
XLVIII
208
XLIX
209
L
213
LI
215
LII
218
LIII
229
LIV
236
LV
245

IX
37
X
38
XI
41
XII
43
XIV
46
XV
50
XVI
71
XVII
72
XIX
77
XX
79
XXI
80
XXII
82
XXIII
85
XXIV
87
XXV
101
XXVI
105
XXVII
108
XXVIII
110
XXIX
111
XXX
115
XXXI
121
XXXII
124
XXXIII
131
XXXIV
135
XXXV
147
XXXVI
153
XXXVII
156
XXXVIII
160
XXXIX
161
XL
165
XLI
166
XLII
175
XLIII
179
XLIV
189
XLV
194
XLVI
197
XLVII
204
LVI
252
LVII
254
LVIII
255
LIX
259
LX
269
LXI
273
LXII
284
LXIII
294
LXIV
299
LXV
306
LXVI
311
LXVII
313
LXVIII
315
LXIX
317
LXX
322
LXXI
327
LXXIII
334
LXXIV
337
LXXV
338
LXXVI
339
LXXVII
341
LXXVIII
346
LXXIX
353
LXXX
358
LXXXI
362
LXXXII
364
LXXXIV
367
LXXXV
368
LXXXVI
370
LXXXVII
377
LXXXVIII
384
LXXXIX
389
XC
395
XCI
403
XCIV
407
XCV
413
Copyright

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Page 11 - ANSI American National Standards Institute ASCII American Standard Code for Information Interchange...
Page 11 - NBS National Bureau of Standards NIST National Institute of Standards and Technology...
Page 407 - A VLIW Architecture for a Trace Scheduling Compiler," Proc. 2nd Int. Conf. Architectural Support for Programming Languages and Operating Systems fASPLOSW,pp.l80-192,Oct. 1987. [FisherSl ] JA Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction,
Page 407 - Deitel, HM and Deitel, PJ, Java: How to Program, Prentice-Hall, Englewood Cliffs, NJ, 1997.

About the author (2017)

John Y. Hsu earned his Ph.D. in computer engineering at the University of California, Berkeley. Dr. Hsu is professor of computer engineering, California Polytechnic State University. He has served as a consultant to Federal Electric/ITT, IBM, and other major corporations.

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